1. Field of the Invention
The present invention relates to a logic description conversion apparatus for and a logic description conversion method of converting a logic description into a more accurate logic description.
2. Description of the Prior Art
In a conventional technique of synthesizing logic, in general, optimum logic is synthesized from a logic description by register extraction means for extracting a corresponding register, Boolean means for processing the logic description by Boolean computation and logic optimization means for optimizing, based on circuit information and timing information for logic optimization, the Boolean logic descriptions which were created by the Boolean means.
In the following, an operation of the present invention will be described in detail. The register extraction means extracts a part of logic descriptions which is described in the register format as a register. Then, the Boolean means processes logic descriptions which are sandwiched between registers or included in a range which is partitioned by input/output ports, that is, logic descriptions other than registers. During the process performed by the Boolean means, whether the logic descriptions are logic of a control computation family or logic of a data computation family (i.e., data transfer family) is not examined. Following this, the logic optimization means optimizes the logic in accordance with the circuit information and the timing information for logic optimization, to thereby generate a logic circuit having optimized logic descriptions.
In the conventional logic synthesis technique, since the Boolean means processes logic descriptions without distinguishing logic descriptions of the control computation family and logic descriptions of the data computation family, if logic synthesis is to be performed on logic descriptions including a sequence circuit, all computation on logic sandwiched between registers must finish within the frequency of a predetermined reference operation clock.
However, as shown in the timing chart of FIG. 17, in reality, while logic computation is carried out at a one-clock frequency T, i.e., the frequency of a reference operation clock, data computation functionlogic ALU between a register reg-A and a register reg-B occasionally requires an especially long three-clock frequency 3T. The data computation family such as the functionlogic ALU is called a multi-clock transfer path in which register-to-register data transfer is not completed within a one-clock frequency but a computation time lingers over a multi-clock period. In FIG. 17, indicated at ST is input control logic of a register, which is formed in correspondence to a register and shows a register load-in enable condition.
FIG. 18 shows a circuit which operates at the timing which is shown in FIG. 17. In FIG. 18, indicated at CLK is a clock input and indicated at DATAIN is a data input. An input control logic group 11 is a logic group which includes ST[0] to ST[3] of FIG. 18. Indicated at reference numeral 12 is a logic group which includes the functionlogic ALU while indicated at reference numeral 13 is a logic group which is controlled by the input control logic ST[0].The registers reg-A and reg-B are basically formed in the D-flip-flop structure. The reference operation clock for the logic circuit shown in FIG. 18 is the one-clock T.
As shown in FIG. 18, the logic group 12 includes the functionlogic ALU of the data computation family and a selector 14 controlled by the input control logic ST[3] of the control computation family. In accordance with ST[3] which is received from an input part P1, the selector 14 selects one of signals which are received from input parts P2 and P3 and outputs the selected signal to a D-input of the register reg-B. The signal which is obtainable from the input part P2 is a Q-output of the register reg-B, and the signal which is obtainable from the input part P3 is a computation result of the functionlogic ALU.
However, with the current logic synthesis technique, it is impossible to control generation of a timing of the selector 14 which is formed in the logic group 12. Hence, if the selector 14 is generated at a relatively early timing point in the three-clock period 3T of the functionlogic ALU of the logic group 12, the signal available from the input part P3 (i.e., a computation result of an unascertained functionlogic ALU) could be selected by the selector 14 before a computation result of the functionlogic ALU is yielded.
In this manner, with the current logic synthesis technique, if logic synthesis is performed on a logic description which includes a multi-clock transfer path which is longer than the reference operation clock, a resulting logic circuit will be different from what is demanded by the specifications, on the contrary to the intention of a designer of the circuit, e.g., the resultant logic circuit could have an extremely slow operation speed.